1. Field of the Invention
The present invention relates to a semiconductor integrated circuit provided with an overvoltage protection circuit for preventing breakdown due to static electricity.
2. Description of the Prior Art
A semiconductor integrated circuit has a structure in which a chip comprised of many semiconductor devices is stored in a package and a pin electrically connected to the chip protrudes beyond the package. When the semiconductor integrated circuit is sorted, packaged, carried, or operated, the chip is electrified positively or negatively due to contact with the exterior objects. Thereafter, when the pin contacts with an electric conductor, static electricity is discharged through a route from the chip to the pin and then the electric conductor. In this case, for example, a gate oxide film of an nMOS transistor of a first-stage input circuit may be broken down in the chip. This phenomenon is referred to as xe2x80x9cbreakdown due to CDM (Charge Device Model). xe2x80x9d
To prevent the breakdown due to CDM, it is necessary to prevent a potential difference from occurring between an input wiring and the ground wiring of the first-stage input circuit. Therefore, it is necessary to set an overvoltage protection circuit for absorbing the potential difference between the input wiring and the ground wiring of the first-stage input circuit.
FIG. 5 is an equivalent-circuit diagram showing the above conventional semiconductor integrated circuit. The semiconductor integrated circuit will be hereafter described by referring to FIG. 5.
In case of a conventional semiconductor integrated circuit, a source electrode 52s of an nMOS transistor 52 constituting an first-stage input circuit 50 is connected to a ground wiring 54 and an overvoltage protection circuit 58 is connected between a ground wiring 56 and a gate electrode 52g of the nMOS transistor 52. The overvoltage protection circuit 58 is comprised of a discharge device 581 having an nMOS transistor structure with which a gate electrode 581g and a source electrode 581s are connected and a discharge device 582 having an nMOS transistor structure with no gate electrode. In case of discharge devices 581 and 582, their respective drain electrodes 581d and 582d are connected to the gate electrode 52g of the nMOS transistor 52 and their respective source electrodes 581s and 582s are connected to the source electrode 52s of the nMOS transistor 52.
A pMOS transistor 60 is provided at the first-stage input circuit 50. The gate electrodes 52g and 60g of the nMOS transistor 52 and the pMOS transistor 60 are connected with an input pad 62 by an input wiring 64. Another overvoltage protection circuit 68 is connected between the ground wiring 56 and an input pad 62. The overvoltage protection circuit 68 has a configuration almost same as that of the overvoltage protection circuit 58 but has a size different from that of the overvoltage protection circuit 58 and is comprised of discharge devices 681 and 682. Parasitic resistances 54r and 56r denote resistance values of ground wirings 54 and 56. A parasitic resistance 64r denotes a resistance value of the input wiring 64. Moreover, the overvoltage protection circuit 68 protects the nMOS transistor 52 from an overvoltage (ESD) mainly applied to the input pad 62. Contact holes 74c, 64c, 54c, 58dc, 58gc, 561c, and 562c, a power-supply wiring 74, and a ground pad 70 will be described later.
FIG. 6 is a top view showing the entire chip of the semiconductor integrated circuit of FIG. 5. Hereafter, description is made by referring to FIGS. 5 and 6. In FIG. 6, a portion same as that of FIG. 5 is provided with the same symbol and their duplicate description is omitted.
In the case of chip 69, ground wirings 54, 56, and 66 are connected to each other nearby the ground pad 70. Therefore, the parasitic resistance 54r denotes the resistance value of the ground wiring 54 from the first-stage input circuit 50 up to the ground pad 70. The parasitic resistance 56r denotes the resistance value of the ground wiring 56 from the overvoltage protection circuit 58 up to the ground pad 70. The ground wiring 54 is used for an first-stage input circuit, the ground wiring 56 is used for a protection circuit, and the ground wiring 66 is used for an internal cell. Moreover, a not-illustrated power-supply wiring is connected to a power-supply pad 72.
FIG. 7 is a top view showing some of the wirings and diffusion layers of the semiconductor integrated circuit of FIG. 5. Hereafter, description will be made by referring to FIGS. 5 to 7. In FIG. 7, however, a portion which is the same as those of FIGS. 5 and 6 is provided with the same symbols and their duplicate description is omitted.
A p+ layer 60p serving as a source region and a drain region is formed on a source electrode 60s and drain electrode 60d of the pMOS transistor 60. An n+ layer 60n serving as a guard ring is formed around the pMOS transistor 60. An n+ layer 52n serving as a source region and a drain region is formed on a source electrode 52s and a drain electrode 52d of the nMOS transistor 52. A p+ layer 52p serving as a guard ring is formed around the nMOS transistor 52. n+ layers 581n and 582n serving as a source region and a drain region are formed on the source electrodes 581s, 582s and the drain electrodes 581d and 582d of the discharge devices 581 and 582. A p+ layer 58P serving as a guard ring is formed around the discharge devices 581 and 582.
The power-supply wiring 74 and the source electrode 60s are connected to each other by the contact hole 74c. The drain electrodes 60d and 52d are connected to each other. The ground wiring 54 and the source electrode 52s are connected each other by the contact hole 54c. The input wiring 64 and the gate electrodes 52g and 60g are connected each other by the contact hole 64c. The input wiring 64 and the drain electrodes 581d and 582d, etc. are connected each other. The ground wiring 56 and the source electrodes 581s and 582s are connected each other by the contact holes 561c and 562c. The source electrodes 581s and 581g are connected each other by the contact hole 58gc. Contact holes 60sc, 60dc, 52sc, 52dc, 581sc, 582sc, and 58dc are used to connect each electrode with each semiconductor layer. The input wiring 64, source electrodes 60s, 52s, 581s, and 582s and drain electrodes 60d, 52d, 581d, and 582d, etc. are formed by patterning the same electrode layer. The ground wirings 54 and 56 and the power-supply wiring 74, etc. are formed by patterning the same wiring layer. The wiring layer is superimposed on the electrode layer through a not-illustrated insulating film. The contact holes 74c, 54c, 561c, and 562c are formed on the insulating film.
Then, operations of the overvoltage protection circuit 58 will be described below by referring to FIGS. 5 to 7.
It is assumed that a chip 69 is positively electrified due to static electricity and under this state, a pin (not illustrated) connected to the input pad 62 contacts an electric conductor. Then, the discharge devices 581 and 582 are turned on and static electricity is discharged through a route formed from the ground wirings 54 and 56 to the overvoltage protection circuit 58 and input pad 62. In this case, an overvoltage is generated between the source electrode 52s and the gate electrode 52g of the nMOS transistor 52. To protect the nMOS transistor 52 from the overvoltage, the overvoltage protection circuit 58 operates. That is, the discharge devices 581 and 582 are turned on to absorb the overvoltage between the source electrode 52s and the gate electrode 52g. Thus, the gate-electrode oxide film of the nMOS transistor 52 is prevented from being broken down due to CDM.
Moreover, another conventional example will be shown below. That is, Japanese Patent Application Laid-Open No. 9-139468 discloses a semiconductor device making it possible to adjacently arrange a protecting device and an device to be protected without lowering an electrostatic-breakdown withstand voltage and reduce a dead space in the semiconductor device.
Furthermore, the official gazette of Japanese Patent Application Laid-Open No. 4-30570 discloses a semiconductor device making it possible to securely protect internal circuits from electrostatic noises.
In FIG. 5, two overvoltage protection circuits 58 and 68 are provided. In this case, the overvoltage protection circuit 68 operates mainly when static electricity or the like is applied to the input pad 62 and the overvoltage protection circuit 58 operates when a chip is electrified. That is, the overvoltage protection circuit 68 is used for preventing an ESD (electrostatic discharge damage) and the overvoltage protection circuit 58 is used for preventing the above-described CDM. Therefore, as shown in FIG. 6, the overvoltage protection circuit 68 is set nearby the input pad 62 and the overvoltage protection circuit 58 is set nearby the first-stage input circuit 50 (refer to FIG. 7). Therefore, the parasitic resistance 54r of the ground wiring 54 and the parasitic resistance 56r of the ground wiring 56 are positioned between the contact hole 54c serving as the ground connection end of the first-stage input circuit 50 and the contact holes 561c and 562c serving as ground connection ends of the overvoltage protection circuit 58. Thus, the ground potential of the first-stage input circuit 50 is different from that of the overvoltage protection circuit 58. Thereby, voltages of the parasitic resistances 54r and 56r drop when static electricity is discharged and therefore, the overvoltage protection circuit 58 is not always operated by the voltage between the source electrode 52s and the gate electrode 52g. Therefore, the overvoltage protection circuit 58 may not properly operate.
Thus, it is an object of the present invention to provide a semiconductor integrated circuit having a reliability improved by properly operating an overvoltage protection circuit.
In a semiconductor integrated circuit of the present invention a transistor connected to an input wiring is connected to any one of ground wirings and an overvoltage protection circuit is connected between the ground wiring with which the transistor is connected and the input wiring. The transistor uses a field-effect transistor, bipolar transistor, or static-induction transistor, etc. The field-effect transistor uses an nMOS transistor or pMOS transistor, etc.
When a pin connected to an input pad contacts with an electric conductor while a chip is electrified due to static electricity, the static electricity is discharged from the ground wiring in the chip toward the input pad. In this case, an overvoltage is generated between electrodes of a transistor in the first-stage input circuit connected to the input pad. To absorb the overvoltage, an overvoltage protection circuit is operated.
An overvoltage protection circuit of the prior art is connected between a ground wiring different from a ground wiring to which a transistor is connected and an input wiring. Therefore, a parasitic resistance having the resistance value of each ground wiring is connected between the transistor and the overvoltage protection circuit. Therefore, the overvoltage protection circuit is not always operated by the inter-electrode voltage of the transistor.
On the other hand, an overvoltage protection circuit of the present invention is connected between a ground wiring to which a transistor is connected and an input wiring. Therefore, the resistance value between the transistor and the overvoltage protection circuit is greatly decreased. Accordingly, the overvoltage protection circuit is operated by the inter-electrode voltage of the transistor.
In other words, a semiconductor integrated circuit of the present invention comprises a first ground wiring for a protection circuit and a second ground wiring for a first-stage input circuit extended in parallel, and the source electrode of a field-effect transistor constituting the first-stage input circuit and connected to the second ground wiring, and an overvoltage protection circuit having a two-terminal-device structure for absorbing an overvoltage generated between the gate electrode and the source electrode of the field-effect transistor and provided nearby the field-effect transistor; wherein one terminal of the overvoltage protection circuit is connected to the second ground wiring at the minimum distance.